Engineer 2 Firmware (FPGA)

About the Role

The FPGA Firmware Engineer will develop and maintain FPGA firmware for advanced radar systems, with a strong expertise in Digital Transceiver Modules (DTM) and embedded microcontroller integration. The role involves implementing high-speed digital interfaces, radar signal chains, and real-time control logic for transceiver operation.

Responsibilities

• Design and implement FPGA firmware for radar transmit/receive processing chains.
• Develop RTL using VHDL / Verilog / SystemVerilog for high-performance real-time applications.
• Build and integrate Digital Transceiver Modules (DTM) for TX/RX path control, digital up/down conversion, synchronization, and high-speed data handling.
• Interface with ADC/DAC, RF transceivers, mixers, and timing circuits.
• Develop FPGA logic for:
  • Data framing and buffering
  • Timing and trigger generation
  • PRI/PRF control
  • Pulse shaping and waveform sequencing
• Integrate FPGA with embedded microcontrollers for configuration, telemetry, calibration, and health monitoring.
• Implement communication interfaces such as SPI, UART, I2C, JESD204B/C, LVDS, Ethernet.
• Support clocking architecture, synchronization, and deterministic latency.
• Perform simulation, verification, timing closure, and hardware debugging.
• Collaborate with RF, DSP, and software teams for system-level integration.

Requirements

• Minimum 5 years of experience in firmware/embedded systems/FPGA solution development for military or defense-related clients.
• Must have solid knowledge of radar digital architecture and signal flow.
• Strong experience with Xilinx or Intel/Altera FPGA platforms.
• Proficiency in VHDL/Verilog/SystemVerilog.
• Strong understanding of Digital Transceiver Modules (DTM) architecture and implementation.
• Experience with high-speed serial interfaces and real-time streaming architectures.
• Experience interfacing FPGA with microcontrollers (STM32, ARM Cortex, etc.).
• Experience with clock domain crossing (CDC), reset synchronization, and timing analysis.
• Familiarity with ADC/DAC data capture and RF control.