Senior FPGA Design Engineer

About the Job
EDGE is an advanced technology group established to develop disruptive solutions for defense and beyond. Solving real-world challenges, it is dedicated to bringing innovative technologies and services to market with greater speed and efficiency. Our people are at the core of our business, inspiring us to imagine a new world of endless possibilities. Leveraging advanced technologies such as autonomous capabilities, cyber-physical systems, and directed energy to artificial intelligence, we recognize that changing the fundamentals of the defense industry will take real collaboration and creativity. Join us today to enable a secure future.

Key Accountabilities

• Implement layer 1/PHY radio front-end algorithms for running on FPGA.
• Implement layer 2 algorithms for running on Microcontroller.
• Create and maintain HDL code to implement FPGA solutions.
• Design using combinational-logic-design and synchronous-circuits.
• Write test benches and use verification tools such as ModelSim.
• Develop test bench automation using TCL script.
• Conduct HDL design synthesis and implementation.
• Utilize vendor tools for timing closure, floor planning, and design constraints.
• Develop solutions for real-time embedded systems related to radar and communication links.
• Use vendor design tools such as Libero and/or Vivado.
• Integrate FPGA peripherals and modules such as timers, ADCs, DACs, communication transceivers (I2C, SPI, CAN, etc.), PWM controllers, DDR memories, and LVDS interfaces.
• Use programming languages for MCU, such as C/C++ and assembly languages.
• Build Linux images such as Yocto and FreeRTOS.
• Design and generate BSP for the SoC in use.
• Lead and mentor junior engineers, foster a collaborative environment, and share knowledge.
• Stay up-to-date with advancements in embedded technologies and best practices.
• Utilize a version-controlled environment such as Git or SVN.
• Maintain code writing discipline such as commenting and bug tracking.
• Conduct hardware testing and troubleshooting using oscilloscopes and logic analyzers.

Knowledge/Qualifications & Experience

• Bachelor’s or master's degree in computer science, communication, electronic, or software engineering.
• Minimum 10 years of experience in VHDL code writing.
• Knowledge and understanding of layer 1/PHY and layer 2 radio front-end algorithm implementation.
• Knowledge and understanding of Verilog.
• Knowledge and understanding of Yocto.
• Exposure to DO-254 development methodology.

Skills

• Bug Tracking
• Field-Programmable Gate Arrays (FPGA)
• Hardware Testing
• Layer 2
• Microcontrollers
• PHY
• Physical Layer
• VHDL
• Verilog
• Xilinx Vivado